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NCV4275A 5.0 V, 3.3 V 450 mA Low-Dropout Voltage Regulator with Reset
The NCV4275A is an integrated low dropout regulator designed for use in harsh automotive environments. It includes wide operating temperature and input voltage ranges. The output is regulated at 5.0 V or 3.3 V and is rated to 450 mA of output current. It also provides a number of features, including overcurrent protection, overtemperature protection and a programmable microprocessor reset. The NCV4275A is available in the DPAK and D2PAK surface mount packages. The output is stable over a wide output capacitance and ESR range. The NCV4275A is pin for pin compatible with NCV4275.
Features http://onsemi.com MARKING DIAGRAMS
DPAK, 5-PIN DT SUFFIX CASE 175AA 4275AxG ALYWW
1
5
* * * * * * *
* * *
5.0 V and 3.3 V, 2% Output Voltage Options 450 mA Output Current Very Low Current Consumption Active Reset Output Reset Low Down to VQ = 1.0 V 500 mV (max) Dropout Voltage Fault Protection +45 V Peak Transient Voltage -42 V Reverse Voltage Short Circuit Protection Thermal Overload Protection AEC-Q100 Qualified Pin Compatible with NCV4275 These are Pb-Free Devices
1
1
D2PAK, 5-PIN DS SUFFIX CASE 936A 5
NC V4275Ax
AWLYWWG
1 x A WL, L Y WW G = 5 (5.0 V Output) or 3 (3.3 V Output) = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
Applications
* Auto Body Electronics
I Error Amplifier + - Current Limit and Saturation Sense Q
Pin 1. I 2. RO Tab, 3. GND* 4. D 5. Q * Tab is connected to Pin 3 on all packages
Bandgap Reference Thermal Shutdown D
ORDERING INFORMATION
See detailed ordering and shipping information in the dimensions section on page 17 of this data sheet.
Reset Generator
GND RO
Figure 1. Block Diagram
(c) Semiconductor Components Industries, LLC, 2010
April, 2010 - Rev. 3
1
Publication Order Number: NCV4275A/D
NCV4275A
PIN FUNCTION DESCRIPTION
Pin # 1 2 Symbol I Description Input; Battery Supply Input Voltage. Bypass to ground with a ceramic capacitor. Reset Output; Open Collector Active Reset (accurate when I > 1.0 V). Ground; Pin 3 internally connected to tab.
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN NNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNN N NN NN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN NNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN NNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN NN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
RO 3, Tab 4 5 GND D Reset Delay; timing capacitor to GND for Reset Delay function. Q Output; 2.0%, 450 mA output. Bypass with 22 mF capacitor, ESR < 4.5 (5.0 V Version), 3.5 (3.3 V Version) to ground.
MAXIMUM RATINGS
Input Voltage
Rating
Symbol VI VI VQ VRO IRO VD ID
Min
Max 45 45 16 25 5.0 7.0 2.0 - - - 150 150
Unit V V V V mA V mA kV V V C C
-42 - -1.0 -0.3 -5.0 -0.3 -2.0 4.0 200 1000 -40 -55
Input Peak Transient Voltage Output Voltage Reset Output Voltage Reset Output Current Reset Delay Voltage Reset Delay Current ESD Susceptibility (Note 1) - Human Body Model - Machine Model - Charge Device Model
ESDHBM ESDMM ESDCDM TJ Tstg
Junction Temperature Storage Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC-Q100-002, ESD Machine Model tested per AEC-Q100-003, ESD Charged Device Model tested per AEC-Q100-011, Latch-up tested per AEC-Q100-004.
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OPERATING RANGE
Input Voltage Operating Range, 5.0 V Output Input Voltage Operating Range, 3.3 V Output Junction Temperature VI VI TJ 5.5 4.4 -40 42 42 150 V V C
LEAD TEMPERATURE SOLDERING REFLOW AND MSL (Note 2)
Lead Free, 60 sec-150 sec above 217C Moisture Sensitivity Level TSLD MSL - 1 265 Peak C
THERMAL CHARACTERISTICS
Characteristic DPAK 5-PIN PACKAGE Min Pad Board (Note 3) Junction-to-T (RqJT) ab Junction-to-Ambient (RqJA) D2PAK 5-PIN PACKAGE 0.4 sq. in. Spreader Board (Note 5) Junction-to-T (RqJT) ab Junction-to-Ambient (RqJA) 2. 3. 4. 5. 6. 3.8 74.8 1.2 sq. in. Spreader Board (Note 6) 4.0 41.6 C/W C/W 4.2 100.9 1 Pad Board (Note 4) 4.7 46.8 C/W C/W Test Conditions (Typical Value) Unit
PRR IPC / JEDEC J-STD-020C 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.062 thick FR4. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.062 thick FR4. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.062 thick FR4. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.062 thick FR4.
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ELECTRICAL CHARACTERISTICS (VI = 13.5 V; -40C < TJ < 150C; unless otherwise noted.)
Characteristic Symbol Test Conditions 5.0V Output Voltage Min Output Output Voltage VQ 100 mA v IQ v 400 mA 6.0V v VI v 28V (5.0V Version) 4.4V v VI v 28V (3.3V version) 100 mA v IQ v 200 mA 6.0V v VI v 40V (5.0V Version) 4.4V v VI v 40V (3.3V version) VQ = 0.9 x VQ,typ IQ = 1.0 mA IQ = 1.0 mA, TJ = 25C IQ = 250 mA IQ = 400 mA Dropout Voltage Load Regulation Line Regulation Power Supply Ripple Rejection Temperature Output Voltage Drift Reset Timing D and Output RO Reset Switching Threshold Reset Output Low Voltage Reset Output Leakage Current Reset Charging Current Upper Timing Threshold Lower Timing Threshold Reset Delay Time Reset Reaction Time Thermal Shutdown Shutdown Temperature (Note 8) TSD -- 150 - 210 150 - 210 C 7. Measured when output voltage VQ falls 100 mV below the regulated voltage at VI = 13.5 V. Vdr = VI - VQ.For output voltage set < 4.4 V, Vdr will be constrained by the minimum input voltage. 8. Guaranteed by design, not tested in production. VQ,rt VROL IROH ID,C VDU VDL trd trr -- Rext 5.0 kW, VQ 1.0V VROH = 5.0V VD = 1.0V -- -- CD = 47nF CD = 47nF 4.53 - - 3.0 1.5 0.2 10 - 4.65 0.2 0 5.5 1.8 0.4 16 1.5 4.8 0.4 10 9.0 2.2 0.7 22 4.0 3.0 - - 3.0 0.7 0.2 10 - 3.1 0.2 0 4.0 1.3 0.4 16 1.5 3.2 0.4 10 11 1.6 0.7 22 4.0 V V mA mA V V ms ms Vdr DVQ DVQ PSRR dVQ/dT IQ = 300 mA Vdr = VI - VQ (Note 7) IQ = 5.0 mA to 400 mA DVI = 8.0 V to 32 V, IQ = 5.0 mA fr = 100 Hz, Vr = 0.5 Vpp -- 4.9 5.0 5.1 3.23 3.3 3.37 V Typ Max 3.3V Output Voltage Min Typ Max Unit
Output Voltage
VQ
4.9
5.0
5.1
3.23
3.3
3.37
V
Output Current Limitation Quiescent Current Iq = II - IQ
IQ Iq
450 - - - - - -30 -15 - -
700 140 140 10 23 250 15 5.0 60 0.5
- 200 150 15 35 500 30 15 - -
450 - - - - - -30 -15 - -
700 135 135 10 23 1100 15 5.0 60 0.5
- 200 150 15 35 1170 30 15 - -
mA mA mA mA mA mV mV mV dB mV/K
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NCV4275A
TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version 3.3 V Version
10
10
1 ESR (W)
Stable ESR Region ESR (W) CQ = 22 mF
1
Stable ESR Region CQ = 22 mF
0.1 VQ(nom) = 5.0 V 0.01 0 100 200 300 400
0.1 VQ(nom) = 3.3 V 0.01 0 100 200 300 400
IQ, OUTPUT CURRENT (mA)
IQ, OUTPUT CURRENT (mA)
Figure 2. Output Stability with Output Capacitor ESR
100 100
Figure 3. Output Stability with Output Capacitor ESR
10 10 ESR (W) 1 Stable ESR Region CQ = 1 mF 0.1 VQ(nom) = 5.0 V 0.01 0 100 200 300 400 0.1 0 VQ(nom) = 3.3 V 100 200 300 400 ESR (W)
1
Stable ESR Region CQ = 1 mF
IQ, OUTPUT CURRENT (mA)
IQ, OUTPUT CURRENT (mA)
Figure 4. Output Stability with Output Capacitor ESR
5.2 VI = 13.5 V, RL = 25 W 3.5
Figure 5. Output Stability with Output Capacitor ESR
VQ, OUTPUT VOLAGE (V)
5.1
VQ, OUTPUT VOLAGE (V)
3.4
VI = 13.5 V, RL = 16.5 W
5.0
3.3
4.9 VQ(nom) = 5.0 V 4.8 -40 0 40 80 120 160
3.2 VQ(nom) = 3.3 V 3.1 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 6. Output Voltage VQ vs. Temperature TJ
Figure 7. Output Voltage VQ vs. Temperature TJ
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TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version
6.0 VQ, OUTPUT VOLTAGE (V) VQ, OUTPUT VOLTAGE (V) 5.0 4.0 3.0 2.0 1.0 0.0 0 RL = 25 W, TJ = 25C 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 RL = 16.5 W, TJ = 25C
3.3 V Version
VQ(nom) = 5.0 V 2 4 6 VI, INPUT VOLTAGE (V) 8 10
VQ(nom) = 3.3 V 2 4 6 VI, INPUT VOLTAGE (V) 8 10
Figure 8. Output Voltage VQ vs. Input Voltage VI
1.2 1.0 0.8 0.6 0.4 0.2 VQ(nom) = 5.0 V 0.0 -40 0 40 80 120 160 VI = 13.5 V 1.2 1.0 0.8 0.6 0.4 0.2
Figure 9. Output Voltage VQ vs. Input Voltage VI
IQ, OUTPUT CURRENT LIMITATION (A)
IQ, OUTPUT CURRENT LIMITATION (A)
VI = 13.5 V
VQ(nom) = 3.3 V 0.0 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 10. Output Current IQ vs. Temperature TJ
IQ, OUTPUT CURRENT LIMITATION (A) IQ, OUTPUT CURRENT LIMITATION (A) 1.2 1.0 0.8 TJ = 125C 0.6 0.4 0.2 VQ(nom) = 5.0 V 0.0 0 10 20 30 40 50 TJ = 25C
Figure 11. Output Current IQ vs. Temperature TJ
1.2 1.0 0.8 TJ = 125C 0.6 0.4 0.2 VQ(nom) = 3.3 V 0.0 0 10 20 30 40 50 TJ = 25C
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 12. Output Current IQ vs. Input Voltage VI
Figure 13. Output Current IQ vs. Input Voltage VI
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NCV4275A
TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version
3.5 Iq, CURRENT CONSUMPTION (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VQ(nom) = 5.0 V 0 20 40 60 80 100 120 IQ, OUTPUT CURRENT (mA) VI = 13.5 V, TJ = 25C Iq, CURRENT CONSUMPTION (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VQ(nom) = 3.3 V 0 20 40 60 80 100 120 IQ, OUTPUT CURRENT (mA) VI = 13.5 V, TJ = 25C
3.3 V Version
Figure 14. Current Consumption Iq vs. Output Current IQ
80 Iq, CURRENT CONSUMPTION (mA) 70 60 50 40 30 20 10 0 0 100 200 300 VQ(nom) = 5.0 V 400 500 600 IQ, OUTPUT CURRENT (mA) VI = 13.5 V, TJ = 25C Iq, CURRENT CONSUMPTION (mA) 80 70 60 50 40 30 20 10 0 0
Figure 15. Current Consumption Iq vs. Output Current IQ
VI = 13.5 V, TJ = 25C
VQ(nom) = 3.3 V 100 200 300 400 500 600 IQ, OUTPUT CURRENT (mA)
Figure 16. Current Consumption Iq vs. Output Current IQ
8 IDC, CHARGE CURRENT (mA) IDC, CHARGE CURRENT (mA) 7 6 5 4 3 2 1 0 -40 0 40 80 VQ(nom) = 5.0 V 120 160 VI = 13.5 V, VD = 1.0 V 6 5 4 3 2 1 0 -40
Figure 17. Current Consumption Iq vs. Output Current IQ
VI = 13.5 V, VD = 1.0 V
VQ(nom) = 3.3 V 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 18. Charge Current ID,C vs. Temperature TJ
Figure 19. Charge Current ID,C vs. Temperature TJ
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NCV4275A
TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version
VDU/VDL, UPPER/LOWER TIMING THRESHOLD (V)
2.0 VDU/VDL, UPPER/LOWER TIMING THRESHOLD (V) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 0
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 0
3.3 V Version
VDU VI = 13.5 V
VDU VI = 13.5 V
VDL VQ(nom) = 5.0 V 40 80 120
VDL VQ(nom) = 3.3 V 40 80 120 160
160
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 20. Delay Switching Threshold VDU, VDL vs. Temperature TJ
700 Vdr, DROPOUT VOLTAGE (mV) 600 500 400 300 200 100 0 0 100 200 300 400 VQ(nom) = 5.0 V 500 600 700 TJ = 25C TJ = 125C
Figure 21. Delay Switching Threshold VDU, VDL vs. Temperature TJ
IQ, OUTPUT CURRENT (mA)
Figure 22. Drop Voltage Vdr vs. Output Current IQ
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NCV4275A
APPLICATION INFORMATION
II CI1 1000 F CI2 100 nF ID CD 47 nF D IQ CQ 22 F RO IRO Rext 5.0 k VRO
VI
I
1 NCV4275A 4 3 GND Iq
5
Q
VQ
2
Figure 23. Test Circuit
Circuit Description The NCV4275A is an integrated low dropout regulator that provides 5.0 V or 3.3 V, 450 mA protected output and a signal for power on reset. The regulation is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. The output current capability is 450 mA, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. The regulator is protected by both current limit and thermal shutdown. Thermal shutdown occurs above 150C to protect the IC during overloads and extreme ambient temperatures. The delay time for the reset output is adjustable by selection of the timing capacitor. See Figure 23, Test Circuit, for circuit element nomenclature illustration. Regulator The error amplifier compares the reference voltage to a sample of the output voltage (VQ) and drives the base of a PNP series pass transistor by a buffer. The reference is a bandgap design to give it a temperature-stable output. Saturation control of the PNP is a function of the load current and input voltage. Over saturation of the output power device is prevented, and quiescent current in the ground pin is minimized. Regulator Stability Considerations The input capacitors (CI1 and CI2) are necessary to stabilize the input impedance to avoid voltage line influences. Using a resistor of approximately 1.0 W in series with CI2 can stop potential oscillations caused by stray inductance and capacitance. The output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum, aluminum or ceramic capacitors can be used. The range of stability versus capacitance, load current and capacitive ESR is illustrated in Figures 2 to 5. Minimum ESR for CQ = 22 mF is native
ESR of ceramic capacitors. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the capacitance and ESR of the capacitor will vary considerably. The capacitor manufacturer's data sheet usually provides this information. The value for the output capacitor CQ shown in Figure 23, Test Circuit, should work for most applications; however, it is not necessarily the optimized solution. Stability is guaranteed for CQ 22 mF and an ESR 4.5 W (5.0 V Version), 3.5 W (3.3 V Version). ESR characteristics were measured with ceramic capacitors and additional resistors to emulate ESR. Murata ceramic capacitors were used, GRM32ER71A226ME20 (22 mF, 10 V, X7R, 1210), GRM31MR71E105KA01 (1 mF, 25 V, X7R, 1206). Reset Output The reset output is used as the power on indicator to the microcontroller. This signal indicates when the output voltage is suitable for reliable operation of the controller. It pulls low when the output is not considered to be ready. RO is pulled up to VQ by an external resistor, typically 5.0 kW in value. The input and output conditions that control the Reset Output and the relative timing are illustrated in Figure 24, Reset Timing. Output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. The delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0.0 V to the upper timing threshold voltage VDU. The charging current for this is ID,C and D pin voltage in steady state is typically 3.2 V for 5.0 V regulator and typically 2.4 V for 3.3 V regulator. By using typical IC parameters with a 47 nF capacitor on the D pin, the following time delay for 5.0 V regulator is derived: tRD = CDVDU / ID,C tRD = 47 nF (1.8 V) / 5.5 mA = 15.4 ms Other time delays can be obtained by changing the capacitor value.
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NCV4275A
VI
t
VQ
< Reset Reaction Time VQ,rt t Reset Charge Current dVD + CD dt Upper Timing Threshold VDU Lower Timing Threshold VDL t Reset Delay Time Reset Reaction Time
VD
VRO
t Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output
Figure 24. Reset Timing
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Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 25) is:
PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max)Iq
(1)
is the maximum input voltage, is the minimum output voltage, is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
T RqJA + 150 C * A PD
(2)
where VI(max) VQ(min) IQ(max)
Heatsinks A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(3)
where RqJC is the junction-to-case thermal resistance, RqCS is the case-to-heatsink thermal resistance, RqSA is the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D.
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in Equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
II VI SMART REGULATOR(R) IQ VQ
} Control Features
Iq
Figure 25. Single Output Regulator with Key Performance Parameters Labeled
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Thermal Model A discussion of thermal modeling is in the ON Semiconductor web site: http://www.onsemi.com/pub/collateral/BR1487-D.PDF.
Table 1. DPAK 5-Lead Thermal RC Network Models
Drain Copper Area (1 oz thick) (SPICE Deck Format) 168 mm2 168 mm2 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd 1.00E-06 1.00E-05 6.00E-05 1.00E-04 4.36E-04 6.77E-02 1.51E-01 4.80E-01 3.740 10.322 168 mm2 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE: Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd 0.015 0.08 0.4 0.2 2.97519 8.2971 25.9805 46.5192 17.7808 0.1 736 mm2 736 mm2 1.00E-06 1.00E-05 6.00E-05 1.00E-04 3.64E-04 1.92E-02 1.27E-01 1.018 2.955 0.438 736 mm2 0.015 0.08 0.4 0.2 2.6171 1.6778 7.4246 14.9320 19.2560 0.1758 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Units W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C R's 0.0123 0.0585 0.0304 0.3997 3.115 3.571 12.851 35.471 46.741 R's 0.0123 0.0585 0.0287 0.3772 2.68 1.38 5.92 7.39 28.94 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 168 mm2 Tau 1.36E-08 7.41E-07 1.04E-05 3.91E-05 1.80E-03 3.77E-01 3.79E+00 2.65E+01 8.71E+01 736 mm2 Tau 1.361E-08 7.411E-07 1.029E-05 3.737E-05 1.376E-03 2.851E-02 9.475E-01 1.173E+01 8.59E+01 Units sec sec sec sec sec sec sec sec sec sec Cauer Network Foster Network
Bold face items represent the package without the external thermal system. Junction R1 R2 R3 Rn
C1
C2
C3
Cn Ambient (thermal ground)
Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values.
Figure 26. Grounded Capacitor Thermal Network ("Cauer" Ladder)
Junction R1 R2 R3 Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC-product time constant; amplitudes are the resistances.
Ambient (thermal ground)
Figure 27. Non-Grounded Capacitor Thermal Ladder ("Foster" Ladder)
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Table 2. D2PAK 5-Lead Thermal RC Network Models
Drain Copper Area (1 oz thick) (SPICE Deck Format) 241 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd 241 mm2 mm2 788 mm2 653 mm2 Units W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C R's C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 0.0123 0.0585 0.0257 0.3413 1.77 1.54 4.13 6.27 60.80 R's 0.0123 0.0585 0.0260 0.3438 1.81 1.52 3.46 5.03 29.30 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 241 mm2 Tau 1.361E-08 7.411E-07 1.005E-05 3.460E-05 7.868E-04 7.431E-03 2.786E+00 2.014E+01 1.134E+02 788 mm2 Tau 1.361E-08 7.411E-07 1.007E-05 3.480E-05 8.107E-04 7.830E-03 2.012E+00 2.601E+01 1.218E+02 Units sec sec sec sec sec sec sec sec sec sec Cauer Network Foster Network
1.00E-06 1.00E-05 6.00E-05 1.00E-04 2.82E-04 5.58E-03 4.25E-01 9.22E-01 1.73 7.12 241 mm2
1.00E-06 1.00E-05 6.00E-05 1.00E-04 2.87E-04 5.95E-03 4.61E-01 2.05 4.88 1.31 653 mm2
R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE:
Junction node1 node2 node3 node4 node5 node6 node7 node8 node9
node1 node2 node3 node4 node5 node6 node7 node8 node9 gnd
0.015 0.08 0.4 0.2 1.85638 1.23672 9.81541 33.1868 27.0263 1.13944
0.0150 0.0800 0.4000 0.2000 1.8839 1.2272 5.3383 18.9591 13.3369 0.1191
Bold face items represent the package without the external thermal system.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula:
R(t) +
S Ri 1-e-t taui i+1
n
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110 100 90 qJA (C/W) qJA (C/W) 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz 110 100 90 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz
Figure 28. qJA vs. Copper Spreader Area, DPAK 5-Lead
Figure 29. qJA vs. Copper Spreader Area, D2PAK 5-Lead
100 Cu Area 167 mm2 10 R(t) C/W Cu Area 736 mm2
1.0 sqrt(t) 0.1
0.01 0.0000001
0.000001
0.00001
0.0001
0.001
0.01 TIME (sec)
0.1
1.0
10
100
1000
Figure 30. Single-Pulse Heating Curves, DPAK 5-Lead
100 Cu Area 167 mm2 10 R(t) C/W Cu Area 736 mm2
1.0
0.1
0.01 0.0000001
0.000001
0.00001
0.0001
0.001
0.01 TIME (sec)
0.1
1.0
10
100
1000
Figure 31. Single-Pulse Heating Curves, D2PAK 5-Lead
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NCV4275A
100 50% Duty Cycle RqJA 736 mm2 C/W 10 20% 10% 5% 2% 1%
1.0
0.1 Non-normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000
PULSE WIDTH (sec)
Figure 32. Duty Cycle for 1" Spreader Boards, DPAK 5-Lead
100 50% Duty Cycle RqJA 788 mm2 C/W 10 20% 10% 5% 2% 1%
1.0
0.1 Non-normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000
PULSE WIDTH (sec)
Figure 33. Duty Cycle for 1" Spreader Boards, D2PAK 5-Lead
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NCV4275A
EMC-Characteristics: Conducted Susceptibility Acceptance Criteria
All EMC-Characteristics are based on limited samples and no part of production test according to 47A/658/CD IEC62132-4 (direct Power Injection).
Test Conditions
Supply Voltage Vin = 12 V Temperature TA = 23C 5C Load RL = 100 W
Direct Power Injection
Amplitude Dev. max 4% of Output Voltage Reset outputs remain in correct state 1 V 1. dBm means dB mili-Watts, P(dBm) = 10 log (P(mW)). 2. A global pin carries a signal or power which enters or leaves the application board. 3. A local pin carries a signal or power which does not leave the application board. It remains on the application board as a signal between two components.
33 dBm (Note 1) forward power CW for global pin (Note 2) 17 dBm (Note 1) forward power CW for local pin (Note 3)
L1 FERRITE L3 FERRITE
X1 VIN_DC
X5 VOUT_DC
X2 VIN_HF
C2 10 mF
C1 100 nF NCV4275A 1I 2 RO Q5 D 4
C4 47 nF
C5 22 mF
X6 VOUT_HF
VOUT
L2 FERRITE
GND U1 3
L4 FERRITE
X3 RO_DC
X7 D_DC
X4 RO_HF
R1 4.99k VOUT
C6 47 nF
X8 D_HF
Figure 34. Test Circuit
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NCV4275A
40 40
30 (dBm)
Vin Pass 33 dBm (dBm)
30
Vout Pass 33 dBm
20
20
10
10
0
1
10
100
1000
0
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. Typical Vin Pin Susceptibility
25 20 15 10 5 0 RO Pass 17 dBm 25 20 15 10 5 0
Figure 36. Typical Vout Pin Susceptibility
(dBm)
1
10
100
1000
(dBm)
Delay Pass 17 dBm
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 37. Typical RO Pin Susceptibility
Figure 38. Typical Delay Pin Susceptibility
ORDERING INFORMATION
Device NCV4275ADS50G NCV4275ADS50R4G NCV4275ADT50RKG NCV4275ADS33G NCV4275ADS33R4G NCV4275ADT33RKG 3.3 V Output Voltage 5.0 V Package D2PAK (Pb-Free) DPAK (Pb-Free) D2PAK (Pb-Free) DPAK (Pb-Free) Shipping 50 Units/Rail 800 Tape & Reel 2500 Tape & Reel 50 Units/Rail 800 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCV4275A
PACKAGE DIMENSIONS
DPAK 5, CENTER LEAD CROP DT SUFFIX CASE 175AA-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.020 0.028 0.018 0.023 0.024 0.032 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.045 BSC 0.170 0.190 0.185 0.210 0.025 0.040 0.020 --- 0.035 0.050 0.155 0.170 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.51 0.71 0.46 0.58 0.61 0.81 4.56 BSC 0.87 1.01 0.46 0.58 2.60 2.89 1.14 BSC 4.32 4.83 4.70 5.33 0.63 1.01 0.51 --- 0.89 1.27 3.93 4.32
-T- B V R C E
SEATING PLANE
R1 Z U
S
A
1234 5
K F L D G
5 PL
J H 0.13 (0.005) T
DIM A B C D E F G H J K L R R1 S U V Z
M
SOLDERING FOOTPRINT*
6.4 0.252 2.2 0.086
5.8 0.228
0.34 5.36 0.013 0.217
10.6 0.417
0.8 0.031
SCALE 4:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCV4275A
PACKAGE DIMENSIONS
D2PAK, 5 LEAD DS SUFFIX CASE 936A-02 ISSUE C
-T- A K B
12345 OPTIONAL CHAMFER TERMINAL 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN
E V
U
S H M L
D 0.010 (0.254)
M
T
N G R
P
C
SOLDERING FOOTPRINT*
8.38 0.33 1.702 0.067 10.66 0.42
DIM A B C D E G H K L M N P R S U V
16.02 0.63
3.05 0.12
1.016 0.04
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative
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NCV4275A/D

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